• UltraScale architecture : For cores running in FEC Enabled mode (8,110.08, 10,137.6, 12,165.12, and 24,330.24 Mb/s), the additional delay is 15 datapath clock cycles which equates to 990 UI with a 64-bit datapath.
• The additional delay added by the RS-FEC is 214 datapath clock cycles which equates to 14124 UI with a 64-bit datapath, plus the fraction of a clock cycle delay that is added to the RX datapath latency by the FEC input gearbox (between 0 and 65UI). See FEC Status Register (0x1B) for details.