Cores Supporting Hard FEC Enabled Mode - 8.11 English

• UltraScale+ architecture : For Hard FEC enabled cores running a non-FEC linerate, the additional delay through the core is 13 datapath clock cycles. This equates to 462 UI with a 64-bit datapath. For cores running with a FEC Enabled line rate, the additional delay through the core is 18 datapath clock cycles, which equates to 1188 UI with a 64-bit datapath.

• The additional delay added by the Hard FEC is 38 datapath clock cycles and equates to 2508 UI with a 64-bit datapath, plus the variable component of the Hard FEC latency, which is added by the Hard FEC alignment process. This is between 135 and 295 datapath clock cycles. See Hard FEC Variable Latency Register (0x20) for details .