This section includes information about using Xilinx tools to customize and generate the core in the Vivado Design Suite.
For Versal™ ACAPs, the core should be used in Vivado IP integrator, because this is the only supported flow to allow IP integrator Block Automation to generate and correctly configure Versal ACAP Transceiver cores. This is also required to enable transceiver sharing with other IP cores.
For UltraScale+™, UltraScale™, and 7 series families either IP integrator flow or the Vivado Integrated Design Environment flow can be used to customize and generate the core.
If you are customizing and generating the core in the IP integrator, see the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) [Ref 8] for detailed information.
IP integrator might auto-compute certain configuration values when validating or generating the design. To check whether the values do change, see the description of the parameter in this chapter. To view the parameter value, run the validate_bd_design command in the Tcl console.
You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core using the following steps:
1. Either select the IP from the Vivado IP catalog or place the CPRI IP core on the IP integrator canvas, depending on which Vivado flow you are using.
2. Double-click the selected IP or select the Customize IP command from the toolbar or right-click menu.
For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 9] and the Vivado Design Suite User Guide: Getting Started (UG910) [Ref 10] .
Note: Figures in this chapter are illustrations of the CPRI ™ configuration screens in the Vivado Integrated Design Environment (IDE). This layout might vary from the current version.
This Figure shows the Vivado IDE configuration tab for the CPRI core.