FIFO Fill Level Register (0x17) - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2022-11-16
Version
8.11 English
Table 2-23: FIFO Fill Level Register

Bits

Description

31:9

Reserved

8:0

FIFO Fill Level

In master cores the starting level of the clock-domain crossing (CDC) FIFO can be set using this register. By default the CDC FIFO fills to fill_level=64 before reading is enabled. The half full level for Standard CDC FIFO depth is 64 and for Extended CDC FIFO is 256. These values maximize the cores ability to buffer against transmission line jitter. To reduce latency, at the expense of reduced cable length support, the FIFO fill level can be reduced.