The CPRI core is generated as encrypted RTL along with unencrypted block layer files. The encrypted RTL contains the transmit and receive logic, control and management interfaces, L1 synchronization logic, and management registers. The block layer contains Versal GT support functions such as GT line rate control and connects the encrypted RTL to an instance of the Versal GT Quad. In addition, optional interfaces for AXI4-Lite management and Open Radio Equipment Interface (ORI) support are provided. There is no shared logic in Versal ACAP CPRI cores.
X-Ref Target - Figure 2-2