For Versal™ ACAPs, ensure that the core is correctly wired up and that Block Automation has been used to connect up the Versal ACAP Transceiver.
• Ensure that all timing constraints for the core were met during implementation.
• Ensure that all clock sources are clean and in particular that the transceiver reference clocks meet the transceiver requirements from the appropriate FPGA Data Sheet.
• Ensure all clock sources are stable before deasserting the external reset signal to the core.
For UltraScale+ and UltraScale devices, ensure that all transceiver PLLs have obtained lock by monitoring the QPLLLOCK_OUT and/or CPLLLOCK_OUT port either using the debug feature or by routing the signals to a spare pin.
• Ensure that all the timing constraints for the core were properly incorporated from the example design and that all constraints were met during implementation.
• Does it work in post-place and route timing simulation? If problems are seen in hardware but not in timing simulation, this might indicate a PCB issue. Ensure that all clock sources are active and clean.
• If using MMCMs in the design, ensure that all MMCMs have obtained lock by monitoring the locked port.
• Disabling the watchdog timer by writing zeros to address 0x15 (AXI 0x54) gives the core the maximum length of time to achieve link-up. In UltraScale devices the watchdog timer is disabled by default.