UltraScale+ architecture: For standalone Hard FEC wrapper IP cores the delay through the Hard FEC wrapper is 38 datapath clock cycles plus the variable delay caused by the Hard FEC alignment process. This is between 135 and 295 datapath clock cycles.
|
Minimum Latency (cycle) |
Maximum Latency (cycles) |
|---|---|
|
38+135 = 173 |
38+295 = 333 |
The CDC FIFO is instantiated in Hard FEC wrapper IP cores and must also be included in any latency calculation. See section Delay Across the CDC FIFO for details.
The delay through the transceiver must also be include in any latency calculation. See section Delay Measurement and Requirement 21 (R21) for details.