Line speed of the core is controlled through the Management Interface. Both the line speed capability for the core and the current line speed use a 15-bit encoding scheme. A description of these bits follows.
• Bit 14: 24,330.24 Mb/s FEC Enabled mode
• Bit 13: 12,165.12 Mb/s FEC Enabled mode
• Bit 12: 10,137.6 Mb/s FEC Enabled mode
• Bit 11: 8,110.08 Mb/s FEC Enabled mode
• Bit 10: 24,330.24 Mb/s
• Bit 9: 12,165.12 Mb/s
• Bit 8: 8,110.08 Mb/s
• Bit 7: 10,137.6 Mb/s
• Bit 6: 9,830.4 Mb/s
• Bit 5: 6,144.0 Mb/s
• Bit 4: 4,915.2 Mb/s
• Bit 3: 3,072.0 Mb/s
• Bit 2: 2,457.6 Mb/s
• Bit 1: 1,228.8 Mb/s
• Bit 0: 614.4 Mb/s
Only one of these bits is set by the core in the current line speed register, indicating the current operating line rate of the core. However, multiple bits of the speed capability register can be set by the managing entity, as described in the following sections.