The core requires information on the frequency of the management clock input (
s_axi_aclk
when using the AXI4-Lite management interface or
aux_clk
otherwise.)
The speed of the clock should be entered in MHz. This ensures the accurate timing of the transceiver reset sequence and calibration of the channel phase-locked loop (CPLL). The management clock can typically run between 10 MHz and 125 MHz. On Artix-7 devices and -2L speed grade Kintex-7 devices, the maximum frequency is 100 MHz. On UltraScale devices the maximum frequency is 125 MHz.