For output generation file location, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 9] .
When the CPRI IP core is generated, the encrypted RTL of the CPRI IP core is output for synthesis and simulation. If the Ethernet option is selected in the CPRI Vivado IDE, the RTL for the FIFO generator and Block Memory Generator are also produced for use in the Ethernet frame buffers. When the AXI IP interface option is selected, the RTL for the
AXI4-Lite IPIF core is also generated. If applicable, the core support level described in
CPRI Core Structure
is generated. The VHDL core support files are output to the
<project_name>.gen/soures_1/ip/<component_name>/synth
directory.