Preferred HDLC Rate Register (0xA) - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2022-11-16
Version
8.11 English
Table 2-9: Preferred HDLC Rate Register

Bits

Description

31:13

Reserved

12:3

HDLC byte valid vector. These bits provide support for the user-defined HDLC rate, see Table: Current HDLC Rate Register . The vector value indicates which bytes in the HDLC codeword contain valid data.

2:0

The preferred HDLC rate for the link. This sets the initial value the core uses in negotiating a common rate with a peer. To ensure correct operation it should be set before link initialization. Typically, this is achieved by disabling the core through the line-speed capability register. For valid values, see Table: Current HDLC Rate Register . Defaults to 480 kb/s.