Product Specification - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

Document ID
Release Date
8.11 English

The CPRI™ core implements Layer 1 and Layer 2 of the CPRI specification in Versal™ ACAP, Zynq ® UltraScale+ MPSoC and RFSoC devices, UltraScale architecture-based, Zynq ® -7000 SoC, and 7 series devices. The CPRI core provides the following client-side interfaces.

I/Q Interface: Consists of a stream of radio data (I/Q samples) that is synchronized to the Universal Mobile Telecommunications System (UMTS) radio frame pulse.

Synchronization Interface: Provides the means for the client logic to synchronize to the network time by transmitting the UMTS radio frame pulse and clock frequency.

High-Level Data Link Control (HDLC) Interface: Transports management information between master and slave. The HDLC interface is serialized and synchronous.

Ethernet Interface: When configured to support speeds of up to 3,072 Mb/s, the Ethernet interface is presented as a Media Independent Interface (MII); this allows a 100 Mb Ethernet Media Access Controller (MAC) to be attached to the core to provide a high-speed channel for management information. When speeds over 4,915.2 Mb/s are supported, a Gigabit Media Independent Interface (GMII) option is available. This allows a 1 Gb Ethernet MAC to be attached to the core. The core includes an Ethernet frame buffer in both transmit and receive directions.

Vendor-Specific Data Interface: Provides client logic access to the vendor-specific sub-channels in the CPRI stream.

Management Interface: Provides control and status registers that allow management of the entire design from a supervisory processor. An AXI4-Lite option is available.

The architecture of the core is shown in This Figure . In addition to the interfaces described previously, the core contains these blocks:

Status/Alarm Block: Reflects the internal state of the core and the state of the link.

Start-up Sequencer: Performs line-rate negotiation and Control and Management (C&M) parameter negotiation at link start-up. This block continuously monitors the state of the link and sends the status to the alarm block.

L1 Synch and CDC : Performs loss of frame and HFN sync detection. The block also passes received data from the recovered clock domain to the CPRI core clock domain.

UMTS Terrestrial Radio Access – Frequency Division Duplexing (UTRA FDD) I/Q Module: A pluggable I/Q module to support multiplexing and demultiplexing of I/Q samples in UTRA FDD systems (shown in This Figure ).

Evolved UMTS Terrestrial Radio Access (E-UTRA) I/Q Module: A pluggable I/Q module to support multiplexing and demultiplexing of I/Q samples in E-UTRA systems (not shown in This Figure ).

Legacy raw I/Q Module: A pluggable I/Q Module for backward compatibility with the raw interfacing timing for CPRI cores (not shown in This Figure ).

Figure 2-1: CPRI Top-Level Block Diagram

X-Ref Target - Figure 2-1