The delay figures given earlier in the section can be used to calculate the link delay, excluding the cable length, from the master synchronization input to the slave synchronization output.
• For 8b10b line rates, 16-bit datapath cores, one datapath clock equates to 20 UI and for 32-bit datapath cores, one datapath clock equates to 40 UI.
• For 64b66b line rates, 32-bit datapath cores, one datapath clock equates to 33 UI and for 64-bit datapath cores, one datapath clock equates to 66 UI.
The delay through the transmitter is equal to the delay through the transmit section of the transceiver plus two datapath clock cycles. The transceiver delays are detailed in the following sections:
• Delay Through the GTXE2 Transceiver
• Delay Through the GTHE2 Transceiver
• Delay Through the GTPE2 Transceiver
• Delay Through the GTHE3 Transceiver
• Delay Through the GTYE3 Transceiver
• Delay Through the GTHE4 Transceiver
• Delay Through the GTYE4 Transceiver
• Delay Through the Versal ACAP GTY Transceiver
The additional two datapath clock cycles represent the latency from the synchronization port to the transceiver input.
In cores supporting line rates of 4,915.2 Mb/s and above, an extra datapath clock cycle should be added, this represents the delay through the scrambler block. In cores running at 10,137.6 Mb/s line rate, an extra three 307.6 MHz datapath clock cycles and one 316.8 MHz datapath clock cycle should be added. These represent the delay through the scrambler block and the delay in clocking data in and out of the transmit CDC FIFO.
The delay through the receiver is equal to the delay through the receive section of the transceiver. In addition the following cycles are added:
• One recovered clock cycle (20 UI in Artix-7 devices) or one datapath clock cycle (Versal ACAP, UltraScale architecture, Virtex-7, and Kintex-7 devices) for the delay from the output of the transceiver into the CDC FIFO.
• (Artix-7 devices only) One recovered clock cycle for delay in converting from 2 bytes to 4 bytes (20 UI).
• One datapath clock cycle latency through the core to the synchronization interface and one datapath clock cycle for clocking the data out of the CDC FIFO.
• In cores supporting line rates of 4,915.2 Mb/s and above, an extra two datapath clock cycles, or recovered clock cycles in Artix-7 devices, should be added. This represents the extra pipeline delay through the receiver.
Adding the delays through the transmit and receive paths together gives the link delay between the master and slave service access points (excluding the cable delay).