Receive CDC FIFO - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2022-11-16
Version
8.11 English

The clock-domain crossing (CDC) receive FIFO in the core includes a circuit to measure the transit time of data across the FIFO.

For Standard CDC FIFO depth, this returns a value in bits 31 to 18 of the R21 Timers register in the management interface (see Table: Management Register Addresses .) This value is a fixed-point representation of the number of datapath clock cycles it takes for data to cross the FIFO. The upper seven bits represent the integer value; the lower seven bits represent the fractional part.

For Extended CDC FIFO depth, the R21 Timers register is not used; instead use the High Resolution FIFO Transit Time registers in the management interface. See the following for details.

In 16-bit datapath cores, this register value can be converted into UI by taking the value held in bits 31 to 18 of the R21 timer register as an unsigned integer, multiplying by 20, and dividing by 128. The multiplication by 20 is due to the FIFO being two 8B/10B code words wide.

For example, a register holds the binary value 10000000000100 (8196 as an unsigned integer). Multiply this value by 20 and divide by 128 to get a transit time of 1,280.625 UI.

In 32-bit datapath cores, the FIFO is four 8B/10B code words wide. The register value can be converted into UI by taking the value held in bits 31 to 18 of the R21 timer register as an unsigned integer, multiplying by 40, and dividing by 128. In cores supporting 64B/66B line rates the register value is converted to UI by multiplying the value by 33 and dividing by 128.

In 64-bit datapath cores, the FIFO is eight bytes wide. The register value can be converted into UI by taking the value in bits 31 to 18 of the R21 timer register, multiplying by 66 and dividing by 128.

The integer and fractional part of the transit time can also be read from the High Resolution FIFO Transit Time (Integer part) and High Resolution FIFO Transit Time (Fractional part) registers in the management interface (see Table: Management Register Addresses ). The register values are converted to UI by first concatenating the integer and fractional parts. The result is then multiplied by 20, 33, 40 or 66, depending on data width and encoding scheme, and divided by 65536.