Supporting Line Rates up to 10,137.6 Mb/s and 12,165.12 Mb/s - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2022-11-16
Version
8.11 English

This Figure shows the clock configuration for a core on an UltraScale architecture supporting line rates up to 10,137.6 Mb/s and 12,165.12 Mb/s. In GTHE3 transceivers, two reference clocks are provided to the QPLL in the GTHE3_COMMON block.

The 307.2 MHz reference is used when operating at line rates of 10,137.6 Mb/s and below.

8,110.08 and 12,165.12 Mb/s operation is supported using an additional 245.76 MHz or 368.64 MHz reference clock.

A single reference clock is provided for GTYE3, GTHE4 and GTYE4 transceivers.

In master mode, the reference clock is generated from a crystal oscillator. In slave mode the reference clock is generated from the recovered clock using an external jitter removal PLL.

Figure 4-10: Core Clock Configuration at 10,137.6/12,165.12 Mb/s (UltraScale Architecture)

X-Ref Target - Figure 4-10

X17376-k8_clocking_10_1376g_re_async_gb.jpg

If the CPLL does not support line rates of 9,830.4 Mb/s then the quad PLL is used at speeds of 8,110.04 Mb/s and above. Otherwise the CPLL is used at 9,830.4 Mb/s and the QPLL at 8,110.08, 10,137.6, and 12,165.12 Mb/s.

At 8,110.08 Mb/s, the quad PLL provides a 4,055.04 MHz clock to the transceiver.

At 9,830.4 Mb/s the quad PLL provides a 4,915.2 MHz clock to the transceiver.

At 10,137.6 Mb/s, the quad PLL provides a 5,068.8 MHz clock to the transceiver.

At 12,165.12 Mb/s, the quad PLL provides a 6,082.56 MHz clock to the transceiver.

The core can use either QPLL0 or QPLL1 from the GTHE3/GTYE3_COMMON block. The qpll_select input to the core should be tied Low when using QPLL0 and High when using QPLL1.

In slave cores, rather than routing the recovered clock directly to the external jitter-removal PLL as shown in This Figure , the recovered clock can be prescaled within the device to a constant nominal rate of 15.36 MHz for all line rates.The example design supplied with the core contains an example implementation of this prescaling technique.

Note: For slave cores the external jitter-removal PLL must free-run in the absence of a reference signal; a PLL that turns off in the absence of a reference causes the transceiver to fail to start up. Contact your local SystemIO specialist for guidance in selecting a PLL for your application.