This Figure shows a suggested clock configuration for a CPRI core on Virtex-7, Zynq-7000 SoC or Kintex-7 devices supporting line rates up to 12,165.12 Mb/s. Two reference clocks are provided to the QPLL in the GTHE2_COMMON block.
The 307.2 MHz reference is used when operating at line rates of 10,137.6 Mb/s and below.
12,165.12 Mb/s operation is supported using an additional 368.64 MHz reference clock (380.16 MHz for GTXE2 devices).
The GTXE2 transceiver does not support operation at 8,110.08 Mb/s. In master mode the reference clocks are generated from a crystal oscillator. In slave mode an external jitter removal PLL should be used to generate the reference clocks from the recovered clock.
The quad PLL is used at line rates of 8,110.08 Mb/s and above.
• At 8,110.08 Mb/s, the quad PLL provides a 4,055.04 MHz clock to the transceiver.
• At 9,830.4 Mb/s, the quad PLL provides a 4,915.2 MHz clock to the transceiver.
• At 10,137.6 Mb/s, the quad PLL provides a 5,068.8 MHz clock to the transceiver.
• At 12,165.12 Mb/s, the quad PLL provides a 6,082.56 MHz clock to the transceiver. This is input to the transceiver through the QPLLCLK input.
The transmitter user clock for the transceiver is provided to the core through clk_316_in port of the IP core. When operating at 64B/66B line rates the frequency of the user clock is 33/32 the frequency of the core clock. The differences in clock frequencies allows for correct operation using the 64B/66B encoding system. The clocking scheme shown in This Figure achieves this by deasserting the clock enable of the global buffer supplying the core clock for one cycle in every 33 clock cycles.
When operating at 8B/10B line rates the frequency of the core clock and clk_316 are the same. The clock enable input of the global buffer supplying the core clock is set High at these line rates.
The recovered clock is routed to the CPRI core by a BUFR in Virtex-7 devices and by a BUFH in Kintex-7 and Zynq-7000 SoC devices. A BUFG is required on the TXOUTCLK output of the transceiver on Kintex-7 and Zynq-7000 SoC devices only.
In slave cores, rather than routing the recovered clock directly to the external jitter-removal PLL as shown in This Figure , the recovered clock can be prescaled within the device to a constant nominal rate of 15.36 MHz for all line rates. The example design supplied with the core contains an example implementation of this prescaling technique.
Note: For slave cores the external jitter-removal PLL must free-run in the absence of a reference signal; a PLL that turns off in the absence of a reference causes the transceiver to fail to start up. Contact your local System I/O specialist for guidance in selecting a PLL for your application.