Supporting Line Rates up to 3,072.0 Mb/s - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

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8.11 English

This Figure shows the clock configuration for a CPRI core on an Artix®-7 device. In master mode, the reference clock is generated from a crystal oscillator. In slave mode the reference is generated from the recovered clock by an external jitter-removal PLL.

Figure 4-6: Core Clock Configuration at 3,072.0 Mb/s (Artix-7 Devices)

X-Ref Target - Figure 4-6


The recovered clock is routed to the CPRI core through a BUFH. The BUFG on the TXOUTCLK output of the transceiver can be replaced by a BUFH in larger Artix-7 devices. See the 7 Series FPGAs Clocking Resources User Guide (UG472) [Ref 6] for details.

The core can use either PLL0 or PLL1 from the GTPE2_COMMON block. The pll_select input to the core should be set to 01 when using PLL0 and to 10 when using PLL1.

In slave cores, rather than routing the recovered clock directly to the external jitter removal PLL as shown in This Figure , the recovered clock can be prescaled within the FPGA to a constant nominal rate of 30.72 MHz for all line rates. The example design supplied with the core contains an example implementation of this prescaling technique.

Note: For slave cores the external jitter-removal PLL must free-run in the absence of a reference signal; a PLL that turns off in the absence of a reference causes the transceiver to fail to start up. Contact your local System I/O specialist for guidance in selecting a PLL for your application.