If the CPLL in the UltraScale device supports line rates over 9,830.4 Mb/s then the CPLL will be used at this line rate. The clocking for 9,830.4 Mb/s capable cores is the same as that shown in This Figure .
This Figure shows the clock configuration for a core on an UltraScale architecture supporting 9,830.4 Mb/s where the CPLL does not support speeds of 9,830.4 Mb/s. In master mode, the reference clock is generated from a crystal oscillator. In slave mode the reference clock is generated from the recovered clock using an external jitter removal PLL.
At line rates up to and including 6,144.0 Mb/s, the channel PLL is used. The quad PLL is used at 9,830.4 Mb/s. The quad PLL is set up to provide a 4,915.2 MHz PLL clock to the transceiver. The core can use either QPLL0 or QPLL1 from the GTHE3/GTYE3_COMMON block. The qpll_select input to the core should be tied Low when using QPLL0 and High when using QPLL1 .
In slave cores, rather than routing the recovered clock directly to the external jitter-removal PLL as shown in This Figure , the recovered clock can be prescaled within the device to a constant nominal rate of 15.36 MHz for all line rates.The example design supplied with the core contains an example implementation of this prescaling technique.
Note: For slave cores the external jitter-removal PLL must free-run in the absence of a reference signal; a PLL that turns off in the absence of a reference causes the transceiver to fail to start up. Contact your local System I/O specialist for guidance in selecting a PLL for your application.