Transceiver Barrel Shift Position Register(0x9) - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

Document ID
PG056
Release Date
2022-11-16
Version
8.11 English
Table 2-8: Transceiver Barrel Shift Position Register

Bits

Description

31:7

Reserved

6:0

Current position of the transceiver receive barrel shifter. See R21 Calculation for more details.

This register is not used for Versal ACAP. The transceiver barrel shift value should be read directly from the Versal GT Quad through an AXI interface.

In UltraScale and 7 series-based cores operating at 8b10b line rates, the current transceiver barrel shift position is reported using this register.