Under certain circumstances it is possible to share the transmit clock logic between several CPRI cores. To share the transmitter clocking the CPRI cores must all operate at the same speed. Attention must also be given to the multi-lane manual mode phase alignment process described in:
• TX Bypass Buffer section of 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 2]
• 7 Series FPGAs GTP Transceivers User Guide (UG482) [Ref 3] .
• UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 4]
• UltraScale Architecture GTY Transceivers User Guide (UG578) [Ref 5]
The transmit phase alignment process will restart when any of the links go down. This resets all the links that share the transmitter clock. The CPRI links are therefore not independent from each other and must be brought up and down together.
One of the cores in the system should be chosen as the master CPRI core for clock sharing and phase alignment (cpri_0 in This Figure ). The txoutclk output from this core is used to generate the overall system clock. This core also initiates TX phase alignment when a reset is received or when one of the links goes down.