This Figure shows the clock configuration for a core on an UltraScale device supporting line rates of 24,330.24 Mb/s, 12,165.12 Mb/s and 8,110.08 Mb/s. GTHE3, 10,137.6 Mb/s and the 8B/10B line rates are not supported in this core configuration. In master mode the 368.64 MHz reference clock is generated from a crystal oscillator. In slave mode the reference clock is generated from the recovered clock using an external jitter removal PLL.
• At 8,110.08 Mb/s, the quad PLL provides a 4,055.04 MHz clock to the transceiver.
• At 12,165.12 Mb/s, the quad PLL provides a 6,082.56 MHz clock to the transceiver.
• At 24,330.24 Mb/s the quad PLL provides a 12,165.12 MHz clock to the transceiver.
The core can use either QPLL0 or QPLL1 from the GTYE3_COMMON block. The qpll_select input to the core should be tied Low when using QPLL0 and High when using QPLL1.
In slave cores, rather than routing the recovered clock directly to the external jitter-removal PLL as shown in This Figure , the recovered clock can be prescaled within the device to a constant nominal rate of 15.36 MHz for all line rates.The example design supplied with the core contains an example implementation of this prescaling technique.
Note: For slave cores the external jitter-removal PLL must free-run in the absence of a reference signal; a PLL that turns off in the absence of a reference causes the transceiver to fail to start up. Contact your local SystemIO specialist for guidance in selecting a PLL for your application.