This Figure shows the structure of the CPRI IP core output products for UltraScale and 7 series architecture-based cores.
The core layer ( <component_name>_block.vhd ) consists of the following components.
• cpri_v8_11.vhd : This is the top level of the encrypted RTL of the CPRI IP core. The RTL contains the logic required to implement the transmit and receive state machines, control and management multiplexing and de-multiplexing, L1 synchronization logic and management registers.
• <component_name>_v7_gtwizard_gt.vhd : In 7 series devices, this file instantiates the transceiver channel primitive. The logic is developed from the output of the serial transceiver wizard.
• <component_name>_rx_sync.vhd : In 7 series devices, this block contains the state machine to perform automatic RX phase and delay alignment for 7 series devices as described in the “RX Buffer Bypass” section of the 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 2] and 7 Series FPGAs GTP Transceivers User Guide (UG482) [Ref 3] .
• <component_name>_v7_gtwizard.vhd : In 7 series devices, this file, derived from the serial transceiver wizard output, instantiates <component_name>_v7_gtwizard_gt together with the receive alignment block.
• <component_name>_gt_and_clocks.vhd : The serial transceiver and clocks block instantiate the transceiver wrappers. Reset handling is also included. A state machine is instantiated that detects a change in line rate by monitoring the status outputs from the encrypted RTL block. When a change in line rate is detected, it reprograms the transceiver clock dividers through the DRP bus. The settings are dependent on the new line rate.
• <component_name>_ori_if.vhd : This file takes the ORI MAC address, port number and, if a slave configuration, the RTWP groups and maps them onto the vendor-specific interface for transmission. In the receive direction the MAC address, port number and, if a master configuration, the RTWP groups are extracted from the vendor-specific data stream and output to the client. See ORI Module for more information.
• <component_name>_axi_lite_ipif_wrapper.vhd : When the AXI interface is selected, this file maps between the generic management interface and the AXI4-Lite interface. See Management Interface and AXI4-Lite Memory Mapped Interface for more information.
• <component_name>_fc32_rs_fec.v : Optional RS-FEC for 64b66b line rates only. See RS-FEC Enabled Mode for more information.
• <component_name>_hard_fec_support.sv : Optional hardened RS-FEC for 64b66b line rates on selected UltraScale+ parts. See Hard RS-FEC Receiver for details.
The core support level ( <component_name>_support.vhd ) consists of the following components.
• <component_name>_clocking.vhd : This file contains the clock logic for the CPRI core. In Zynq-7000 SoC, Virtex-7, Kintex-7, and Artix-7 based designs, an MMCM is used to generate the system clock from the TXOUTCLK output of the transceiver. The MMCM output is routed to the core layer and the user logic through a BUFG. A state machine is included to modify the MMCM clock divider settings using the DRP bus when the line rate of the CPRI link is changed. In UltraScale architecture designs the TXOUTCLK output of the transceiver is routed to the core layer and the user logic through a BUFG_GT. In addition, this file routes the RXOUTCLK output from the transceiver through a clock buffer. The output is used to generate the recovered clock input to the core layer. See the Clock Configuration sections in Design Considerations for more information.
• <component_name>_gt_common.vhd : This file instantiates the transceiver common block. If the core is configured to run at a line rate of 9,830.4 Mb/s, the common block provides the 4,915.2 MHz reference clock for running at 9.8304 Gb/s. When 10,137.6 Mb/s operation is supported the common block provides a 5,068.8 MHz reference clock to the transceiver. When 12,165.12 Mb/s operation is supported the common block provides a 6,082.56 MHz reference clock to the transceiver. When 24,330.24 Mb/s operation is supported the common block provides a 12,165.12 MHz reference clock to the transceiver. In Artix-7 FPGA-based designs the common block contains the PLLs for the transceiver. In other cases the common block is instantiated to correctly set the BIAS_CFG parameter.
• <component_name>_tx_alignment.vhd : This block contains the state machine to perform manual TX phase and delay alignment as described in the “TX Buffer Bypass” section in the UltraScale Architecture GTY Transceivers User Guide (UG578) [Ref 5] , the UltraScale Architecture GTH Transceivers User Guide (UG576) [Ref 4] , 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref 2] and the 7 Series FPGAs GTP Transceivers User Guide (UG482) [Ref 3] .
• <component_name>_resets.vhd : This block contains logic to generate the reset to the transceiver common block.
An example design is provided that shows an example of how to instantiate the CPRI IP core. This is generated when Open IP Example Design is selected. The example design files are generated to the example_project/<component_name>_ex/imports/ directory. See Example Design for more information.