This Figure illustrates the example design that is generated when the core support layer option is enabled.
In the case of a CPRI ™ core including a Hard FEC, additional m(1|2|3)_hard_fec interfaces are provided in the example VHDL wrapper. Up to three CPRI cores with no support layer can make use of the Hard FEC block shared by the host CPRI core.
The complete example design can be opened as a separate project by right-clicking the core in the project hierarchy after it has been customized using the IP catalog. Right-click the <component_name>.xci in the Design Sources hierarchy in the Sources window and select Open IP Example Design . This opens a new Vivado project in a new window with a complete CPRI example design.
The CPRI example design consists of the following:
• An instance of the CPRI core
• An example VHDL wrapper containing data generators and monitors
The example design can be run through the Vivado Implementation flow.
Note: The example design is not intended to be programmed onto a device as there are no device specific pin location constraints included in the example design xdc file.
Additional logic is included within the example design for the following functions:
• Constant Rate Clock Division : The received recovered clock output by the transceiver varies in frequency depending on the line rate set (manually or by auto-negotiation). This logic ensures that a constant clock rate is output to the external jitter-removal PLL.
• Reset Logic for Slave : A top-level input, ext_clk_ok , is provided to allow the state of the external jitter-removal PLL to have influence on the design; specifically, this signal inhibits the hires_clock_ok flag until the external PLL is in LOCKED state.
• Data Generation and Monitoring : Data generators are provided to stimulate the transmit IQ, Ethernet, HDLC, ORI and vendor-specific data interfaces. The data arriving at the receive interfaces is checked against the transmitted data in monitor blocks. Error counters are incremented when mismatches are detected. The operation of the CPRI link can be tested by looping the serial output of the core back to the input and querying the status counters in the data monitors. Data generation and monitoring is enabled when the core is in the operational state.
• Management Register Multiplexing : The monitor blocks provide counters for the number of frames or words received and for the number of errors detected. Multiplexing is included in the example design to enable these counters to be read through the management interface. The top-level example design is intended as a template for you to use in creating your own top-level FPGA design.
The example design consists of the following VHDL source files:
• <component_name>_example_design.vhd : Top-level example design encapsulating a CPRI core together with the data generator and monitor blocks. The example design instantiates the <component_name>_support.vhd file. This includes the CPRI encrypted RTL block along with the core and core support layers. It is expected that <component_name>.vhd is the block that designers instantiate in their design.
• iq_tx_gen.vhd : IQ data generator. This block outputs a simple incrementing data pattern to the core transmit I/Q (Data) interface.
• iq_rx_chk.vhd : IQ data monitor. This block checks the receive I/Q (Data) interface for the incrementing pattern output by the IQ data generator. Error and basic frame counters are provided.
• mii_stim.vhd/gmii_stim.vhd : Ethernet data generator and monitor block. Dummy Ethernet frames are transmitted to the CPRI MII/GMII interface and the frames received are monitored. Transmit and receive frame counters are provided. An error counter is incremented when mismatches between the transmitted and received frames are detected.
• hdlc_stim.vhd : The HDLC block sends a serial bit pattern generated by a pseudo-random binary sequence counter. The received pattern is checked for errors and a counter is incremented if any are detected.
• vendor_stim.vhd : The vendor-specific block outputs words to the vendor-specific interface in sub channels 16 to 19. The words are generated by a pseudo-random binary sequence counter. The received pattern is checked for errors and a counter is incremented if any are detected.
• ori_stim.vhd : An ORI stimulus block outputs and checks the port number and Ethernet MAC address of the core. In slave cores RTWP information is generated and in master cores the RTWP ports are monitored.
This Figure illustrates the example design that is generated when the core support layer option is not selected.
In addition to the blocks described previously, the example design includes logic for clock generation, along with an instance of the transceiver common block and the TX phase and delay alignment circuitry. These additional blocks enable full functionality for a single CPRI link. The following extra VHDL files are instantiated by the example design:
• <component_name>_clocking.vhd . In Zynq®-7000, Virtex-7, Kintex®-7, and Artix®-7 based designs, this block consists of the MMCM and BUFGs required to generate clocks for the System and Recovered clock domains. A state machine is also generated to modify the MMCM divider settings using the DRP bus when a speed change occurs. In UltraScale™ architecture-based designs the block routes the transceiver output clocks to the System and Recovered clock domains through BUFG_GTs. In the case of a CPRI core including a Hard FEC, the transceiver output clock is routed only to the Recovered clock domain through a BUFG_GT. The System clock is now created by an MMCM placed in the example design wrapper. The transmit clock can be shared between multiple CPRI cores. See Transmitter Clock Sharing for a two core example.
• <component_name>_gt_common.vhd : One transceiver common block is required per quad on the FPGA. The clock and reference clock outputs from the block can be shared between all the cores in the quad.
• <component_name>_tx_alignment.vhd : This block carries out the TX phase and delay alignment functions. The block interfaces to the alignment interface described in Transceiver Interface (UltraScale and 7 Series Cores Only) . See Resource Sharing for a two core example.
• cpri_hard_fec_wrapper.vhd : A CPRI Hard FEC Wrapper core is created and connected to the hard_fec interface of the CPRI core. Interfaces m(1|2|3)_hard_fec of the CPRI Hard FEC Wrapper core are left open and could provide Hard FEC functionality to three other CPRI cores.
A user constraints file ( <component_name>_example_design.xdc ) is included to support implementation of the example design.