Using an External GMII Interface - 8.11 English

CPRI LogiCORE IP Product Guide (PG056)

Document ID
Release Date
8.11 English

In designs supporting line rates of 4,915.2 Mb/s and higher, a GMII option is available for the Ethernet interface. If the design is to interface to an off-chip Ethernet MAC then care must be taken to meet the timing requirements specified in IEEE 802.3-2015 [Ref 15] .

In the example design that is delivered with the core, the transmit GMII interface is driven by an Ethernet data generator block. The receive interface is routed to a data monitor. The gmii_if.vhd that is also delivered implements the external GMII interface shown in This Figure .

Figure 4-18: External GMII Interface

X-Ref Target - Figure 4-18


The Ethernet reference clock, eth_ref_clk , runs at 125 MHz in GMII mode. This is forwarded to the Ethernet MAC along with the received GMII data and control signals. An Input/Output Block (IOB) Double Data Rate (DDR) output register is used giving the clock the same clock-to-pad delay as the data and control signals. The forwarded clock is inverted with respect to eth_ref_clk so that its rising edge occurs in the center of the data window. This gives the best possible setup and hold times for driving the external interface.

The eth_tx_clk input to the CPRI core is provided by the GMII_TX_CLK clock received from the Ethernet MAC. This clock is also used to clock the received data and control signals through IOB input buffers. The data and control signals are delayed with respect to the clock. The delay is provided by IODELAY elements which should be set to sample a 2 ns setup, 0 ns hold window at the device pins. The trace tool provides information on the setup and hold window at the device pins.

An IDELAYCTRL primitive should be instantiated to control the IODELAY elements. A suitable reference clock must also be supplied to the IDELAYCTRL. Refer to the appropriate SelectIO™ Resources user guide for the relevant FPGA family: (AM010) [Ref 22] , (UG471) [Ref 19] , or (UG571) [Ref 20] .