This file contains the reset logic for the transceiver common block.
|
Port |
Direction |
Port on CPRI IP Core |
Description |
|---|---|---|---|
|
aux_clk |
In |
N/A |
Management Clock |
|
reset |
In |
N/A |
System Reset |
|
qpll_reset |
Out |
qpllreset_in port of the
|
Reset for the quad PLL |