The
<component_name>_tx_alignment
block performs the transmit phase and delay alignment process for each of the CPRI cores in the system.
Table: Signal Connections for TX Alignment Sharing
describes the ports of the <component_name>_tx_alignment block and shows how to connect them to the four CPRI cores in the system.
Table 4-4:
Signal Connections for TX Alignment Sharing
Port
|
Direction
|
Port on CPRI IP Core
|
Description
|
stable_clock
|
In
|
N/A
|
Management clock
|
reset_phalignment
|
In
|
reset_phalignment output from the chosen master CPRI core
|
Request from the core to start TX phase alignment
|
phase_alignment_done
|
Out
|
phase_alignment_done input of all CPRI cores
|
Asserted High when phase alignment has completed.
|
txdlyreset_vec[3:0]
|
Out
|
txdlysreset input of the respective CPRI core
|
TX Delay Alignment Soft Reset
|
txdlysresetdone_vec[3:0]
|
In
|
txdlysresetdone output of the respective CPRI core
|
Asserted High to Indicate that TX delay alignment soft reset has completed.
|
txphinit_vec[3:0]
|
Out
|
txphinit input of the respective CPRI core
|
TX Phase Alignment initialization
|
txphinitdone_vec[3:0]
|
In
|
txphinitdone output of the respective CPRI core
|
Asserted High to Indicate that TX phase alignment initialization has completed.
|
txphalign_vec[3:0]
|
Out
|
txphalign input of the respective CPRI core
|
Asserted High to set TX phase alignment.
|
txphaligndone_vec[3:0]
|
In
|
txphaligndone output of the respective CPRI core
|
The second rising edge of the txphaligndone signal after txdlysresetdone assertion indicates that TX phase and delay alignment has completed.
|
txdlyen_vec[3:0]
|
Out
|
txdlyen input of
the respective CPRI core
|
Enables the TX delay alignment in manual mode.
|