AXI Crossbar Core Parameters - 2.1 English

NUM_SI^a

1

Integer (1-16)

Number of SI slots.

NUM_MI^(a)

2

Integer (1-16)

Number of MI slots.

ID_WIDTH^(a)

0

Integer (0-32)

Width of all ID signals propagated by the AXI Crossbar core. This is the actual width of ID signals on each MI slot. Each SI slot uses a subset of this width for its thread ID signals, if any.

ADDR_WIDTH^(a)

32

For AXI4 or AXI3:

Integer (12-64);

for AXI4-Lite:
Integer (1-64)

Width of all ADDR signals for all SI slots and MI slots.

DATA_WIDTH^(a)

32

Integer
(32, 64, 128, 256, 512, 1024)

Data width of the internal interconnect Write and Read datapaths.

AWUSER_WIDTH^(a)

0

Integer (0-1024)

Width of awuser signals (if any) for all AXI4 SI slots and MI slots.

ARUSER_WIDTH^(a)

0

Integer (0-1024)

Width of aruser signals (if any) for all AXI4 SI slots and MI slots.

WUSER_WIDTH^(a)

0

Integer (0-1024)

Width of wuser signals (if any) for all AXI4 SI slots and MI slots.

RUSER_WIDTH^(a)

0

Integer (0-1024)

Width of ruser signals (if any) for all AXI4 SI slots and MI slots.

BUSER_WIDTH^(a)

0

Integer (0-1024)

Width of buser signals (if any) for all AXI4 SI slots and MI slots.

CONNECTIVITY_MODE

SAMD

String (SASD,SAMD)

Shared-Access (SASD); Sparse Crossbar (SAMD)

ADDR_RANGES

1

Integer (1-16)

Number of Address Ranges per MI slot

PROTOCOL^(a)

AXI4

String
(AXI4, AXI3, AXI4LITE)

Protocol of all interfaces

R_REGISTER

0

Integer (0, 1)

Enable Read Channel Internal Register Slice (SASD mode only)

STRATEGY

0

Integer (0, 1, 2)

Crossbar Optimization Strategy:

0 = Custom Settings

1 = Minimize Area

2 = Maximize Performance

See AXI Crossbar Core — Global Tab for details.

Snn_BASE_ID ^a b

0

Bit32 (0-0xFFFFFFFF)

Base ID of each SI slot

Snn_THREAD_ID_WIDTH ^{a b}

0

Integer (0-32)

Number of variable low-order ID bits of each SI slot. Each value must be <= ID_WIDTH.

Snn_SINGLE_THREAD

0

Integer (0, 1)

ID-thread support by SI slot:

0 = Accept multiple outstanding thread ID values (performance optimized).

1 = Accept only one outstanding thread ID value at a time (area optimized).

Snn_ARB_PRIORITY

0

Integer (0-16)

Arbitration priority among each SI slot. Higher values indicate higher priority. All slots with value 0 participate in round-robin arbitration.

Snn_WRITE_ACCEPTANCE

2

Integer (1-32)

Number of data-active Write transactions that each AXI SI slot can generate

Snn_READ_ACCEPTANCE

2

Integer (1-32)

Number of active Read transactions that each AXI SI slot can generate

Mmm_Aaa_BASE_ADDR^a

mm * 0x100000 for Mmm_A00_BASE_ADDR, otherwise unused (0xFFFFFFFFFFFFFFFF)

Bit64

Base address of each address range aa (where 0 <= aa <= ADDR_RANGES-1) of each MI slot, mm (where 0 <= mm <= M-1). All low-order bits of base address in the range [Mmm_Aaa_ADDR_WIDTH-1: 0] must be zero.

Mmm_Aaa_ADDR_WIDTH^a

12 for range A00, otherwise 0 (unused)

For AXI4 or AXI3:

Integer (12-64); for AXI4-Lite: Integer (1-64)

Number of address bits representing the address space (in bytes) covered by each address range aa (where 0 <= aa <= ADDR_RANGES-1) of each MI slot, mm (where 0 <= mm <= M-1).

Mmm_Snn_WRITE_
CONNECTIVITY

1

Integer (0, 1)

Enables the pathway between Snn and Mmm for write.

Mmm_Snn_READ_
CONNECTIVITY

1

Integer (0, 1)

Enables the pathway between Snn and Mmm for read.

Mmm_WRITE_ISSUING

4

Integer (1-32)

Number of data-active Write transactions that each AXI4 MI slot can generate

Mmm_READ_ISSUING

4

Integer (1-32)

Number of active Read transactions that each AXI4 MI slot can generate

Mmm_SECURE

0

Integer (0, 1)

Indicates whether each MI slot connects to a secure slave device (allows TrustZone secure access).

0 = non-secure slave device

1 = secure slave device