AXI Data Width Converter

AXI Data Width Converter - 2.1 English

AXI Interconnect LogiCORE IP Product Guide (PG059)

Document ID

PG059

Release Date

2022-05-17

Version

2.1 English

Common Configuration:

•ID Width: 4 (AXI4 and AXI3 only)

•Address Width: 32

•User Width: 0

•Read/Write

Note: The specifications in these tables are derived by implementing the configured IP in isolation, characterizing clock frequency based on static timing results, and then applying a 10% guardband below the highest constrained clock frequency that meets timing.

Table 2-12: AXI Data Width Converter Performance
Protocol	Width Conversion	FIFO Mode	Clock Conversion	SI Data Width	MI Data Width	Performance (MHz)
Protocol	Width Conversion	FIFO Mode	Clock Conversion	SI Data Width	MI Data Width	Virtex-7 and Kintex-7 (and its Zynq-7000 derivatives), Speed Grade -2	Kintex UltraScale, Speed Grade -2	Artix-7 (and its Zynq-7000 derivatives), Speed Grade -2
AXI4 or AXI3	Downsize	n/a	n/a	64-256	< SI width	265	325	175
	Downsize	n/a	n/a	512-1024	< SI width	230	295	155
	Upsize	0 (no FIFO)	n/a	< MI width	64	325	380	215
				< MI width	128-256	260	320	175
				< MI width	512-1024	220	295	145
		1 (FIFO, single clock)	n/a	< MI width	64	325	400	220
				< MI width	128-256	295	355	195
				< MI width	512-1024	230	350	155
		2 (FIFO, dual clock)	Sync or async	< MI width	64	325	400	220
				< MI width	128-256	280	355	190
				< MI width	512-1024	230	325	155
AXI4-Lite	Downsize	n/a	n/a	64	32	350	400	350
AXI4-Lite	Upsize	n/a	n/a	32	64	350	400	350