AXI Data Width Converter Resource Utilization: AXI4 Upsizer

AXI Data Width Converter Resource Utilization: AXI4 Upsizer - 2.1 English

AXI Interconnect LogiCORE IP Product Guide (PG059)

Document ID

PG059

Release Date

2022-05-17

Version

2.1 English

Common Configuration:

•Protocol: AXI4 or AXI3

•SI ID Width: 2

•Address Width: 22

•Target device: xc7vx485t

Table 2-21: AXI Data Width Converter Resource Utilization: AXI4 Upsizer
FIFO Mode	Clock Conversion	MI Data Width	SI Data Width	Read/Write				Read-Only			Write-Only
FIFO Mode	Clock Conversion	MI Data Width	SI Data Width	LUTs	FFs	18k BRAM	36k BRAM	LUTs	FFs	18k BRAM	LUTs	FFs	36k BRAM
No FIFO	None	64	32	580	590	0	0	270	320	0	310	270	0
		128	32–64	830	940	0	0	390	520	0	440	420	0
		256	32–128	1300	1620	0	0	600	910	0	700	710	0
		512	32–256	2070	2980	0	0	1010	1690	0	1060	1290	0
		1024	32–512	4010	5680	0	0	1820	3230	0	2190	2450	0
Packet FIFO	None	64	32	860	810	2	1	470	440	2	390	370	1
		128	32–64	1030	870	4	2	490	450	4	540	420	2
		256	32–128	1430	970	8	4	530	460	8	900	510	4
		512	32–256	2040	1140	16	8	600	470	16	1440	670	8
		1024	32–512	3280	1480	32	16	650	470	32	2630	1010	16
Packet FIFO with Clock Conversion	Sync (Any Ratio)	64	32	860	820	2	1	470	440	2	390	380	1
		128	32–64	1040	880	4	2	490	460	4	550	420	2
		256	32–128	1430	980	8	4	540	460	8	890	520	4
		512	32–256	2060	1160	16	8	600	470	16	1460	690	8
		1024	32–512	3290	1500	32	16	650	480	32	2640	1020	16
	Async	64	32	980	1280	2	1	510	640	2	470	640	1
		128	32–64	1140	1340	4	2	520	650	4	620	690	2
		256	32–128	1520	1440	8	4	560	650	8	960	790	4
		512	32–256	2160	1620	16	8	630	660	16	1530	960	8
		1024	32–512	3390	1960	32	16	680	670	32	2710	1290	16