AXI Interconnect Core I/O Signals

AXI Interconnect Core I/O Signals - 2.1 English

AXI Interconnect LogiCORE IP Product Guide (PG059)

Document ID

PG059

Release Date

2022-05-17

Version

2.1 English

Table: AXI Interconnect Core Slave I/O Signals lists the Slave Interface signals for the AXI Interconnect core. In the Signal Name column “nn” represents a two-digit sequence number (with leading zero) with range 00 <= nn <= N-1, where N refers to the total number of configured Slave Interfaces, which is the number of master devices connected to the AXI Interconnect core. Each row in the table therefore defines N interface signals. When a range of values is specified in the Width column, the signal width is determined by the tools based on system connectivity.

Table 2-27: AXI Interconnect Core Slave I/O Signals
Signal Name	Direction	Default	Width	Description (Range)
Snn_ACLK	Input	REQ	1	Slave interface clock input
Snn_ARESETN	Input	REQ	1	Slave interface reset input (active-Low)
Snn_AXI_AWID	Input	AXI3, AXI4: 0 AXI4-Lite: d/c	[1–32]	Write Address Channel Transaction ID
Snn_AXI_AWADDR	Input	REQ	[12–64]	Write Address Channel Address
Snn_AXI_AWLEN	Input	AXI3, AXI4: 0 AXI4-Lite: d/c	AXI4: 8 AXI3: 4	Write Address Channel Burst Length (0–255)
Snn_AXI_AWSIZE	Input	AXI3, AXI4: REQ⁽¹⁾ AXI4-Lite: d/c	3	Write Address Channel Transfer Size code (0–7)
Snn_AXI_AWBURST	Input	AXI3, AXI4: REQ⁽¹⁾ AXI4-Lite: d/c	2	Write Address Channel Burst Type code (0–2).
Snn_AXI_AWLOCK	Input	AXI3, AXI4: 0 AXI4-Lite: d/c	AXI4: 1 AXI3: 2	Write Address Channel Atomic Access Type (0, 1)
Snn_AXI_AWCACHE	Input	AXI3, AXI4: 0⁽²⁾ AXI4-Lite: d/c	4	Write Address Channel Cache Characteristics
Snn_AXI_AWPROT	Input	0b000⁽³⁾	3	Write Address Channel Protection Bits
Snn_AXI_AWQOS⁽⁴⁾	Input	AXI4: 0 AXI4-Lite: d/c	4	AXI4 Write Address Channel Quality of Service
Snn_AXI_AWUSER	Input	AXI3, AXI4: 0 AXI4-Lite: d/c	[1–1024]	User-defined AW Channel signals
Snn_AXI_AWVALID	Input	REQ	1	Write Address Channel Valid
Snn_AXI_AWREADY	Output		1	Write Address Channel Ready
Snn_AXI_WID	Input	AXI3: 0 AXI4, AXI4-Lite: d/c	[1–32]	Write Data Channel Transaction ID for AXI3 masters
Snn_AXI_WDATA	Input	REQ	[32, 64, 128, 256, 512, 1024]	Write Data Channel Data
Snn_AXI_WSTRB	Input	all ones	[32, 64, 128, 256, 512, 1024] / 8	Write Data Channel Byte Strobes
Snn_AXI_WLAST	Input	AXI3, AXI4: 0 AXI4-Lite: d/c	1	Write Data Channel Last Data Beat
Snn_AXI_WUSER	Input	AXI3, AXI4: 0 AXI4-Lite: d/c	[1–1024]	User-defined W Channel signals
Snn_AXI_WVALID	Input	REQ	1	Write Data Channel Valid.
Snn_AXI_WREADY	Output		1	Write Data Channel Ready.
Snn_AXI_BID	Output		[1–32]	Write Response Channel Transaction ID.
Snn_AXI_BRESP	Output		2	Write Response Channel Response Code (0–3).
Snn_AXI_BUSER	Output		[1–1024]	User-defined B Channel signals.
Snn_AXI_BVALID	Output		1	Write Response Channel Valid.
Snn_AXI_BREADY	Input	REQ	1	Write Response Channel Ready.
Snn_AXI_ARID	Input	AXI3, AXI4: 0 AXI4-Lite: d/c	[1–32]	Read Address Channel Transaction ID.
Snn_AXI_ARADDR	Input	REQ	[12–64]	Read Address Channel Address.
Snn_AXI_ARLEN	Input	AXI3, AXI4: 0 AXI4-Lite: d/c	AXI4: 8 AXI3: 4	Read Address Channel Burst Length code (0–255).
Snn_AXI_ARSIZE	Input	AXI3, AXI4: REQ⁽¹⁾ AXI4-Lite: d/c	3	Read Address Channel Transfer Size code (0–7).
Snn_AXI_ARBURST	Input	AXI3, AXI4: REQ⁽¹⁾ AXI4-Lite: d/c	2	Read Address Channel Burst Type (0–2).
Snn_AXI_ARLOCK	Input	AXI3, AXI4: 0 AXI4-Lite: d/c	AXI4: 1 AXI3: 2	Read Address Channel Atomic Access Type (0, 1).
Snn_AXI_ARCACHE	Input	AXI3, AXI4: 0⁽²⁾ AXI4-Lite: d/c	4	Read Address Channel Cache Characteristics.
Snn_AXI_ARPROT	Input	0b000⁽³⁾	3	Read Address Channel Protection Bits.
Snn_AXI_ARQOS⁽⁴⁾	Input	AXI4: 0 AXI4-Lite: d/c	4	AXI4 Read Address Channel Quality of Service.
Snn_AXI_ARUSER	Input	AXI3, AXI4: 0 AXI4-Lite: d/c	[1–1024]	User-defined AR Channel signals.
Snn_AXI_ARVALID	Input	REQ	1	Read Address Channel Valid.
Snn_AXI_ARREADY	Output		1	Read Address Channel Ready.
Snn_AXI_RID	Output		[1–32]	Read Data Channel Transaction ID.
Snn_AXI_RDATA	Output		[32, 64, 128, 256, 512, 1024]	Read Data Channel Data.
Snn_AXI_RRESP	Output		2	Read Data Channel Response Code (0–3).
Snn_AXI_RLAST	Output		1	Read Data Channel Last Data Beat.
Snn_AXI_RUSER	Output		[1–1024]	User-defined R Channel signals.
Snn_AXI_RVALID	Output		1	Read Data Channel Valid.
Snn_AXI_RREADY	Input	REQ	1	Read Data Channel Ready.
Notes: 1.Xilinx recommends that AXI4 master devices drive their aw/rsize and aw/rburst outputs. Typically, a master device drives an aw/rsize value that corresponds to its interface data width, unless application requirements dictate otherwise. Typically, a master device drives its aw/rburst output to 0b01, which indicates an incremental (INCR) burst. 2.Xilinx recommends that master devices drive their aw/rcache outputs to 0b0011 to allow the AXI Interconnect core to pack data while performing width conversion. 3.AXI protocol requires master devices to drive their aw/rprot output. If the aw/rprot signals are left undriven, it defaults to all zeros and the transaction is interpreted as secure. 4.Although the QOS signals are defined only by the AXI4 protocol specification, this interconnect IP core also propagates QOS signals for any SI slot configured as AXI3.