These limitations apply to the AXI Interconnect core and all applicable infrastructure cores:
•The AXI Interconnect core does not support discontinued AXI3 features:
°Atomic locked transactions. This feature was retracted by the AXI4 protocol. A locked transaction is changed to a non-locked transaction and propagated by the MI.
°Write interleaving. This feature was retracted by AXI4 protocol. AXI3 master devices must be configured as if connected to a slave with a Write interleaving depth of one.
•AXI4 Quality of Service (QoS) signals do not influence arbitration priority in AXI Crossbar. QoS signals are propagated from SI to MI.
•AXI Interconnect cores do not support low-power mode or propagate the AXI C channel signals.
•AXI Interconnect cores do not time out if the destination of any AXI channel transfer stalls indefinitely. All connected AXI slaves must respond to all received transactions, as required by AXI protocol.
•AXI Interconnect (AXI Crossbar core) provides no address remapping.
•AXI Interconnect sub-cores do not include conversion or bridging to non-AXI protocols, such as APB.
•AXI Interconnect cores do not have clock-enable (aclken) inputs. Consequently, the use of aclken is not supported among memory-mapped AXI interfaces in Xilinx systems.
Note: The aclken signal is supported for Xilinx AXI4-Stream interfaces.