AXI Register Slice Parameters - 2.1 English

AXI Interconnect LogiCORE IP Product Guide (PG059)

Document ID: PG059
Release Date: 2022-05-17
Version: 2.1 English

Table: AXI Register Slice Parameters lists the parameters specific to the AXI Register Slice core.

Table 3-15: AXI Register Slice Parameters
Parameter Name	Default Value	Format/Range	Description
REG_AW	Light	String (Bypass, Full, Light, SI_Reg). SLR Crossing, SLR TDM Crossing, Multi SLR Crossing	Mode of channel register slice⁽¹⁾
REG_W	For AXI4 or AXI3: Full For AXI4-Lite: Light	String (Bypass, Full, Light, SI_Reg). SLR Crossing, SLR TDM Crossing, Multi SLR Crossing	Mode of channel register slice⁽¹⁾
REG_B	Light	String (Bypass, Full, Light, SI_Reg). SLR Crossing, SLR TDM Crossing, Multi SLR Crossing	Mode of channel register slice⁽¹⁾
REG_AR	Light	String (Bypass, Full, Light, SI_Reg). SLR Crossing, SLR TDM Crossing, Multi SLR Crossing	Mode of channel register slice⁽¹⁾
REG_R	For AXI4 or AXI3: Full For AXI4-Lite: Light	String (Bypass, Full, Light, SI_Reg). SLR Crossing, SLR TDM Crossing, Multi SLR Crossing	Mode of channel register slice⁽¹⁾
Notes: 1.Bypass: SI pins of channel are directly wired to MI. Full: Implemented as a 2-deep FIFO buffer, supporting throttling by the channel source and/or destination as well as back-to-back transfers without incurring bubble cycles. Light: Implemented as a simple 1-stage pipeline register, minimizing resources while isolating timing paths, but always incurring 1 bubble cycle following each transfer. SI_Reg/MI_Reg: Passes the VAILID handshake input and all payload inputs on the source side through simple flip-flops; supports back-to-back transfers.