AXI Register Slices - 2.1 English

AXI Interconnect LogiCORE IP Product Guide (PG059)

Document ID
PG059
Release Date
2022-05-17
Version
2.1 English

You can optionally insert AXI Register Slice cores on selected pathways between the SI, crossbar and MI within the AXI Interconnect core, as needed, to break critical timing paths and achieve higher clock frequency. For more information, see AXI Register Slice Parameters. You can also instantiate the AXI Register Slice core directly in your design (without AXI Interconnect core) along any pathway between an AXI master and slave device.

For complete descriptions of all operating modes available in the stand-alone Register Slice core, see AXI Register Slice LogiCORE IP Product Guide (PG373) [Ref 16].