The Width Conversion core performs an upsizer function whenever the data width on the MI side is wider than on the SI side. Data packing is performed (for incr and wrap bursts), provided the AW/ARCACHE[1] bit (“Modifiable”) is asserted.
In the resulting transaction issued to the MI side, the number of data beats is reduced accordingly.
•For Writes, data merging occurs on the W-channel between the SI and MI.
•For Reads, data serialization occurs on the R-channel between the MI and SI.
The AXI Interconnect core replicates the rresp from each MI-side input data beat onto the rresp of each SI-side output data beat.
See Table: AXI Data Width Converter Functional Truth Table and Table: AXI Data Width Converter Transaction Transformation Formulae for details on the upsizing transformations for various configurations and transaction types.
When the AW/ARCACHE[1] bit is deasserted, the transaction (address channel values) remains unchanged and data transfers pass through unchanged except for byte-lane steering. This latter functionality is commonly referred to as an “expander.” Upsizing never results in transaction splitting.
The AXI Data Width Converter core allows multiple outstanding transactions to be propagated (AXI4 and AXI3 protocols only). Transaction characteristics from the AW/AR channel transfers are queued while awaiting corresponding response transfers. However, due to the possibility of read data re-ordering, transactions issued on the MI side of the Data Width Converter are restricted to a reordering depth of 1 (single ID thread). As a result, the currently active transaction ID is stored internally and no ID signals are present on the MI. This eliminates the need for downstream IP cores to store and process ID information, saving logic.
When upsizing transfers in AXI3 and AXI4 protocol, the Data Width Converter IP core can also perform FIFO buffering. When this option is enabled, data merging on the W-channel and serialization on the R-channel is integrated into the FIFO buffer by using the asymmetrical block RAM feature of the FPGA. When FIFO buffering is enabled, the Data Width Converter IP core can also perform synchronous or asynchronous clock frequency conversion. (See Clock Conversion for available features.) Asynchronous clock conversion is integrated into the FIFO buffer by using the dual-clock feature of the FIFO. Integrating width conversion and optional clock conversion into the FIFO results in reduced latency and significantly reduced register utilization compared with implementing the same functions separately. When enabled, buffering is performed using the 512-deep “packet FIFO mode” (store and forward) method on both write and read channels. (See AXI Data FIFO for details.) When using the AXI Interconnect core in IP integrator, the IP core automatically recognizes opportunities to combine requested FIFO buffering and required clock conversion into the Data Width Converter IP core for datapaths that require upsizing.
When the Width Converter is configured in FIFO mode, it functions as a packet-mode FIFO, as described in the AXI Data FIFO section. That means propagation of AW channel transfers get delayed until complete write data bursts are stored in the FIFO, and AR channel transfers will get delayed as the FIFO fills until there is sufficient vacancy to accept the whole read data burst. Unlike the AXI Data FIFO, a fixed number of transactions can be accommodated in the FIFO, regardless of the actual length of the bursts, due to the width conversion function being performed. The FIFO is always implemented with a depth of 512 (single BRAM block), as viewed on the wider MI interface. When configured to upsize the data width by a factor of 2, there are only 4 burst buffers implemented in the FIFO. When configured to upsize by any larger ratio, there will be 8 buffers implemented. This will, in turn, limit the maximum number of transactions the Data Width Converter can issue to the number of buffers minus one. Furthermore, burst buffers only become free, allowing more commands to be issued, only after each data burst is completely read from the output side of the FIFO.
When configured for AXI4-Lite protocol, the Data Width Converter provides for upsizing from 32-bit to 64-bit AXI4-Lite transfers. Each SI transaction always results in one MI transaction; no data packing is performed.
You can also instantiate the AXI Data Width Converter core directly in your design (without AXI Interconnect core) along any pathway between a narrow AXI master device and a wider AXI slave.