AXI4-to-AXI3 Converter - 2.1 English

AXI Interconnect LogiCORE IP Product Guide (PG059)

Document ID
PG059
Release Date
2022-05-17
Version
2.1 English

An AXI4 master device can be connected through an AXI Protocol Converter core to an AXI3 slave. The Protocol Converter also produces the required WID output on the MI based on the AWID received at the SI.

By default, any time a burst longer than 16 data beats is received, the command is split into several shorter burst transactions. Other than that, the address channel characteristics are not modified by the Protocol Converter (the data transfer size is never modified).

The AXI3 converter module normally allows multiple outstanding transactions to be propagated. Transaction characteristics from the AW/AR channel transfers are queued while awaiting corresponding response transfers.

However, due to the possibility of write response and read data re-ordering, transaction acceptance by the Protocol Converter (while in AXI3 conversion mode) is dynamically reduced to a single outstanding transaction at a time (for each of the write and read directions) whenever a transaction requires splitting. (Unlike Data Width Converter, ID signals are always propagated between SI and MI, regardless of splitting.)

When directly instantiating the Protocol Converter IP core, the TRANSLATION_MODE parameter can be set to 0 (Unprotected) to save resources when AXI3 slaves are accessed only by well-behaved masters that issue transactions that never exceed 16 data beats (after any intervening width conversion).