Crossbar Signal Interface - 2.1 English

AXI Interconnect LogiCORE IP Product Guide (PG059)

Document ID
PG059
Release Date
2022-05-17
Version
2.1 English

The interface of the AXI Crossbar core consists of a single, vectored AXI SI, plus a single, vectored AXI MI. Each vectored interface can be configured to connect to between 1 and 16 master/slave devices. The pathways connecting to all the Slave Interfaces of the AXI Interconnect core are merged together to connect to the vectored SI interface of the AXI Crossbar. The pathways connecting to all the Master Interfaces of the AXI Interconnect core are merged together to connect to the vectored MI interface of the AXI Crossbar.

For each signal comprising a vectored AXI interface on the AXI Crossbar core, its natural width is multiplied by the number of devices to which it is connected. All of the bit slices that connect to a single device are referred to as a slot of the interface. For example, the awsize signal carries a 3-bit value indicating the number of bytes transferred during each data beats in a Write transaction. If the AXI Crossbar core is configured with two SI slots, the s_axi_awsize signal is a total of 6-bits wide.

In cases where the number of used bits varies from slot to slot (such as the number of S_AXI_AWID bits received from each connected master), the stride of the vectored signal is typically the maximum configured signal width among all the slots. (See the I/O signal tables in Port Descriptions for details.) The unused bit positions are then tied off (inputs) or trimmed (outputs).

For example, if the AXI Crossbar core is configured with two SI slots and a data width of 128 bits, then each of the wdata and rdata signals on the SI of the core is a total of 256 bits wide, as shown in This Figure.

Figure 3-1:      Vectored Slave/Master Interface

X-Ref Target - Figure 3-1

pg059_crossbar_interface_x13094.jpg

Specifically:

“slot 0” uses wdata[127:0] 

“slot 1” uses wdata[255:128], and connects to wdata[127:0] of the “Master 1” device).

If you instantiate the AXI Crossbar core directly into a design, you should tie off unused bit positions to zero to avoid synthesis and/or simulation warnings. When connecting to a read-only or write-only master or slave device, you should tie off all input bit positions corresponding to unused write or read channels, respectively.