Debugging - 2.1 English

AXI Interconnect LogiCORE IP Product Guide (PG059)

Document ID
PG059
Release Date
2022-05-17
Version
2.1 English

A common system malfunction that you can encounter when designing with any IP core with AXI interfaces can occur when custom IP (or non-production version of an IP) violates AXI protocol rules. Xilinx AXI IP cores do not contain any logic to guard against AXI protocol violations incurred by IP cores to which they are connected.

One of most common symptoms of an AXI protocol violation in a system is an apparent lock-up of a connected core. The AXI Interconnect core and the contained Crossbar core are especially vulnerable to protocol violations incurred by connected IP cores. When such a lock-up condition occurs, it often appears that an AXI channel transfer (VALID/READY handshake) completes on one interface of the Interconnect, but the resultant transfer is never issued on the expected output interface. Other possible symptoms include output transfers that appear to violate AXI transaction ordering rules.

 

RECOMMENDED:   Xilinx strongly recommends that you use the available protocol checker IP core to test for AXI protocol compliance before deploying any custom IP or IP with custom modifications.

The clock conversion IP core, including Data Width Converter configured in FIFO Mode, can perform either synchronous or asynchronous clock conversion. When configured for synchronous conversion, it is required that the SI and MI clocks remain edge-aligned at all times. When using a Clock Wizard IP core to generate the AXI clocks, make sure the actual output clock frequencies maintain an integer-ratio relationship (1:2, 1:3... 1:16), as the actual frequency can differ from the requested frequency for each clock.

If the active edges of the SI and MI clocks drift apart during operation, you might observe a malfunction of the clock conversion IP core, including dropped transfers or lock-up. Xilinx clock conversion IP cores do not contain any logic to guard against misalignment of clock edges when configured in synchronous conversion mode. To help isolate a clock edge misalignment, reconfigure the clock conversion IP core to perform asynchronous conversion. If system functionality is restored, you should investigate the SI and MI clock waveforms for misalignment (or continue using asynchronous conversion, if acceptable).

This appendix includes details about resources available on the Xilinx Support website and debugging tools.