Debugging Guidance for AXI Interconnect Cores in the IP Integrator - 2.1 English

AXI Interconnect LogiCORE IP Product Guide (PG059)

Document ID
PG059
Release Date
2022-05-17
Version
2.1 English

IP integrator provides additional system and IP automation facilities which can, from time to time, cause you to encounter new warnings or error messages. Typically such warnings and errors are presented when the configuration of one IP core in a design is incompatible with the configuration of an IP core to which it has been connected.   In many cases, the AXI Interconnect core will automatically attempt to resolve differences in the configuration of the master and slave IP cores to which it has been connected by adding a conversion IP core within the interconnect instance itself. To see which IP cores have been automatically added, use the Expand hierarchy buttons in the IP integrator canvas to explore within the AXI Interconnect instance's hierarchy.

Figure B-1:      Vivado IP Integrator Expand Hierarchy with AXI Interconnect Core

X-Ref Target - Figure B-1

expand_hierarchy.png

Note:   IP integrator supports only "read-only" viewing of the contents of the AXI Interconnect core.   It is possible to open the configuration Vivado IDE of each IP core within the AXI Interconnect instance to see its detailed configuration but the values cannot be changed.

If unexpected converter IP core instances are discovered while inspecting the AXI Interconnect core hierarchy, it is recommended to review the interface properties of the AXI Master or AXI slave connected to the AXI Interconnect core.   The AXI interface properties of an IP interface can be seen by first selecting the interface on the IP core then opening the IP integrator Block Interface Properties panel (select Window > Properties from the Vivado menu bar if the properties panel is not currently shown).

Figure B-2:      Vivado IP Integrator Block Interface Properties Window Showing AXI Interface Properties

X-Ref Target - Figure B-2

slave_interfaces_tab00014.png

The interface properties of the AXI Master or Slave should be compared with the interface properties of the corresponding AXI Crossbar instance within the AXI Interconnect core.   Certain differences in the values of the interface properties lead to the automatic addition of converter IP cores within the AXI Interconnect core.   For example, if the DATA_WIDTH property differs between the AXI Master and the AXI Crossbar, a data width converter IP core will be inserted.   If a conversion IP core is not desired, the configuration Vivado IDE of the AXI Master or AXI Slave IP core should be used to change the configuration of the IP core such that its interface properties are consistent with those found on the connected AXI Crossbar interface.