Features - 2.1 English

AXI Interconnect LogiCORE IP Product Guide (PG059)
Document ID
PG059
Release Date
2022-05-17
Version
2.1 English

The AXI Interconnect core is comprised of multiple LogiCORE IP instances (infrastructure cores). Each of the AXI4 memory-mapped infrastructure cores that comprise the AXI Interconnect core are fully described in this document. The following features apply to the AXI Interconnect core in general and to all infrastructure cores described in this document unless otherwise noted:

•AXI protocol compliant. Can be configured to support AXI3, AXI4, and AXI4-Lite protocols.

•Interface data widths:

°AXI4 and AXI3: 32, 64, 128, 256, 512, or 1,024 bits

°AXI4-Lite: 32 or 64 bits

•Address width: Up to 64 bits

•USER width (per channel): Up to 1,024 bits

•ID width: Up to 32 bits

•Support for Read-only and Write-only masters and slaves, resulting in reduced resource utilization.

LogiCORE IP Facts Table

Core Specifics

Supported Device Family(1)

UltraScale+™,

UltraScale™,
7 Series FPGAs

Zynq®-7000

Supported User Interfaces

AXI4, AXI4-Lite, AXI3

Resources

See Table: AXI Crossbar Resource Utilization: SAMD, AXI4 Protocol  through Table: AXI Register Slice Resource Utilization.

Provided with Core

Design Files

Verilog and VHDL

Example Design

Not Provided

Test Bench

Not Provided

Constraints File

Xilinx Design Constraints (XDC)

Simulation Model

Not Provided

Supported
S/W Driver

N/A

Tested Design Flows(2)

Design Entry

Vivado® Design Suite

Simulation

For supported simulators, see the
Xilinx Design Tools: Release Notes Guide

Synthesis

Vivado Synthesis

Support

Release Notes and Known Issues

Master Answer Records: 54453

All Vivado IP Change Logs

Master Vivado IP Change Logs: 72775

Xilinx Support web page

Notes:

1.For a complete list of supported devices, see the Vivado IP catalog. Support for the AXI Interconnect IP is not migrated beyond the UltraScale+ family. AXI switching for the Versal family and beyond should instead use the AXI Smartconnect IP, which provides compatible functionality. For more information, see PG247 [Ref 15]. Also, support does not extend beyond the UltraScale+ family for any the AXI infrastructure cores covered in this Product Guide, except AXI Register Slice.

2.For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide.