The tables in this section summarize the estimated maximum performance for various modules within the AXI Interconnect core. These values were generated using the Vivado® Design Suite. The values are derived from post-implementation timing reports after implementing the example design generated for each IP configuration. The overall performance of a given instance of AXI Interconnect is limited by the clock frequencies of all constituent modules. Visit Xilinx Support web page and search for PG059 for additional performance data for the individual infrastructure cores.
The following devices were used to obtain the results:
•Artix®-7: xc7a200tfbg676-2
These results also apply to Zynq®-7000 devices based on the Artix-7 fabric, as described in DS187 [Ref 12].
•Kintex®-7: xc7k325tffg900-2
These results are also indicative of the expected performance of Virtex®-7 devices.
•Zynq®-7000: xc7z045ffg900-2
These results were combined with the xc7k325-2 results and represent Zynq-7000 devices based on the Kintex-7 fabric, as described in DS191 [Ref 13].
•Kintex UltraScale™: xcku085-flva1517-2