N-to-M Interconnect (Crossbar Mode) - 2.1 English

AXI Interconnect LogiCORE IP Product Guide (PG059)

Document ID
PG059
Release Date
2022-05-17
Version
2.1 English

The N-to-M use case of the AXI Interconnect core, when in Crossbar mode, features a Shared-Address Multiple-Data (SAMD) topology, consisting of sparse data crossbar connectivity, with single, shared Write and Read address arbitration, as shown in This Figure and This Figure.

Figure 2-4:      Shared Write and Read Address Arbitration

X-Ref Target - Figure 2-4

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Figure 2-5:      Sparse Crossbar Write and Read Data Pathways

X-Ref Target - Figure 2-5

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Parallel Write and Read data pathways connect each SI slot to all the MI slots that it can access, according to the configured sparse connectivity map. When more than one source has data to send to different destinations, data transfers can occur independently and concurrently, provided AXI ordering rules are met. By disabling unused paths, datapath multiplexing logic and address decoding logic can be reduced, resulting in reduced FPGA resource utilization and faster timing paths.

The Write address channels among all SI slots feed into a central address arbiter, which grants access to one SI slot at a time. It is also the case for the Read address channels. The winner of each arbitration cycle transfers its address information to the targeted MI slot, and pushes an entry into the appropriate command queue(s) that enable various data pathways to route data to the proper destination while enforcing AXI ordering rules. Crossbar mode is available only when AXI Crossbar is configured for AXI4 or AXI3 protocol.