Other AXI Infrastructure Core Parameters - 2.1 English

AXI Interconnect LogiCORE IP Product Guide (PG059)

Document ID
PG059
Release Date
2022-05-17
Version
2.1 English

This section defines the configuration parameters for the following AXI Infrastructure cores:

AXI Data Width Converter Parameters

AXI Clock Converter Parameters

AXI Protocol Converter Parameters

AXI Data FIFO Parameters

AXI Register Slice Parameters

AXI MMU

Table: AXI Infrastructure Common Parameters lists the parameters common to all AXI Infrastructure cores, unless otherwise noted.

Table 3-10:      AXI Infrastructure Common Parameters

Parameter Name

Default Value

Format/

Range

Description

ID_WIDTHa

0

Integer (0-32)

Width of all ID signals propagated by the core. Except Data Width Converter core.

ADDR_WIDTH(a)

32

For AXI4 or AXI3: Integer (12-64); for AXI4-Lite: Integer (1-64)

Width of all addr signals. Except AXI MMU core.

DATA_WIDTH(a)

32

 For AXI4 or AXI3: Integer
(32, 64, 128, 256, 512, 1024); for AXI4-Lite: Integer (32, 64)

Data width of the Write and Read datapaths. Except AXI Data Width Converter core.

AWUSER_WIDTH(a)

0

Integer (0-1024)

Width of awuser signals (if any). Except Data Width Converter core.

ARUSER_WIDTH(a)

0

Integer (0-1024)

Width of aruser signals (if any). Except Data Width Converter core.

WUSER_WIDTH(a)

0

Integer (0-1024)

Width of wuser signals (if any). Except Data Width Converter core.

RUSER_WIDTH(a)

0

Integer (0-1024)

Width of ruser signals (if any). Except Data Width Converter core.

BUSER_WIDTH(a)

0

Integer (0-1024)

Width of buser signals (if any). Except Data Width Converter core.

READ_WRITE_MODE(a)

READ_WRITE

String (READ_WRITE, READ_ONLY, WRITE_ONLY)

Enables read channels and/or write channels

PROTOCOL(a)

AXI4

String (AXI4, AXI3, AXI4LITE)

Protocol of all interfaces. Except AXI Protocol Converter core.

aAutomatically set by tools based on system connectivity