Except for Register Slice configured for SLR Crossing, there are no constraints required for any cores covered in this Product Guide. Floor planning Constraints for Register Slice SLR Crossing Modes When using the Register Slice core in either the SLR Crossing, SLR TDM Crossing or Multi SLR Crossing mode, constraints can be applied to explicitly floorplan the submodules of the core into adjacent SLRs. This will ensure that the SLR crossing(s) will take place between the intended flop-to-flop, unit-fanout, internal wires across all payload and handshake pathways within the core. After synthesis, all logic and registers that should be placed into the master-side SLR (where the AXI master connected to the SI interface is located) will contain the cell name pattern *slr_master*. All logic and registers that should be placed into the slave-side SLR (where the AXI slave connected to the MI interface is located) will contain the cell name pattern *slr_slave*. When spanning 3 SLRs, all logic and registers that should be placed into the instance name of the Register Slice and any of these sub-module name patterns can then be used to group all cells in the core into their respective PBLOCKs for floorplanning. In the following example, a Register Slice instance named my_reg is configured in Multi SLR Crossing mode (all channels) to cross two SLR boundaries that exist in the target device. One of the boundaries exists between row Y4 (the top of the lower SLR) and row Y5 (the bottom of the middle SLR). The other boundary exists between row Y9 (the top of the middle SLR) and row Y10 (the bottom of the upper SLR).
create_pblock lower_slr
add_cells_to_pblock [get_pblocks lower_slr] [get_cells -hierarchical -filter "NAME=~*my_reg*slr_master*"]
resize_pblock [get_pblocks lower_slr] -add {CLOCKREGION_X0Y0:CLOCKREGION_X5Y4} create_pblock center_slr
add_cells_to_pblock [get_pblocks center_slr] [get_cells -hierarchical -filter "NAME=~*my_reg*slr_middle*"]
resize_pblock [get_pblocks center_slr] -add {CLOCKREGION_X0Y5:CLOCKREGION_X5Y9} create_pblock upper_slr
add_cells_to_pblock [get_pblocks upper_slr] [get_cells -hierarchical -filter "NAME=~*my_reg*slr_slave*"]
resize_pblock [get_pblocks upper_slr] -add {CLOCKREGION_X0Y10:CLOCKREGION_X5Y14}