The tables in this section indicate the estimated FPGA resource utilization for various modules within the AXI Interconnect core. These values were generated using Vivado Design Suite. They are derived from post-synthesis reports, and might change implementation.
Some typical configurations of each module are listed. The overall area of a given instance of AXI Interconnect can be estimated by accumulating the utilizations of all constituent modules.
Note: UltraScale™ architecture results are expected to be similar to 7 series device results.