Revision History - 2.1 English

05/17/2022

2.1

General Updates

11/29/2017

2.1

Added configuration modes to AXI Register Slice to cross SLRs in SSI devices.

04/05/2017

2.1

•Added Registered Input to the AXI Register Slices section in Chapter 3.

•Added SI_Reg and MI_Reg to parameters in the AXI Register Slice Parameters section in Chapter 3 and to the Register Slice Options section in Chapter 4.

•Added SI_Reg/MI_Reg description to the note in Table 3-15.

•Added the Timing Closure of AXI Memory-Mapped Connections Across SLRs in SSI Devices section to Chapter 4.

•Added Automotive Disclaimer.

04/06/2016

2.1

•Updated Kintex UltraScale performance information to Tables 2-10 through Table 2-14.

•Updated Table 2-1 through Table 2-15.

•Added new AXI MMU section.

•Modified the ID Width to be 4 for the AXI Clock Converter, AXI Data FIFO, AXI Protocol Converter, and AXI Register Slice sections.

•Added a note about the table specifications in the AXI Data FIFO, AXI Data Width Converter, AXI Protocol Converter, and AXI Register Slice sections.

•Updated the Common Configuration items in the AXI Crossbar Performance: SAMD, AXI4 Protocol, AXI Crossbar Performance: SASD, AXI4 Protocol, and AXI Crossbar Performance: SASD, AXI4-Lite Protocol sections.

•Updated the device part numbers in the Maximum Performance section.

11/18/2015

2.1

Added support for UltraScale+ families.

04/01/2015

2.1

•Changes were made to the following sections in Chapter 3, Designing with the Core: Address Decode, Transaction Arbitration, AXI Upsizer, and AXI MMU Parameters.

•Added AXI MMU section.

10/01/2014

2.1.1

Document only update.

•Removed the following sentence from page 8:
“Write and Read transactions are multiplexed to AXI4-Lite slave devices, propagating only a single address at a time, which typically avoids the duplication of logic resources otherwise associated with separate AXI write and read address signals.”

•Added text to the Transaction Arbitration section on page 74.

•Removed Figure 3-2, Cascading AXI Interconnect Cores, and associated text.

•Modified text on page 89 in the last sentence of the first paragraph in the Conversion to AXI4-Lite section.

05/17/2022

2.1

General updates

04/02/2014

2.1

Added support for example design generation.

Added AXI MMU.

12/18/2013

2.1

Added UltraScale™ architecture support.

10/02/2013

2.1

•Revision number advanced to 2.1 to align with core version number 2.1.

•Added support for example design generation.

•Updated Figures 4-1 through 4-5 in Chapter 4.

•Added the options Thread ID Width and Synchronization Stages.

•Updated information in the Migrating and Upgrading appendix.

•Updated the descriptions of Snn_HAS_REGSLICE, Mnn_HAS_REGSLICE and NUM_MI.

•Updated Figure B-1.

•Added Maximum Performance section to Chapter 2.

03/20/2013

1.2

Updated Vivado Design Suite and core version 2.0.

Updated Appendix B, Debugging.

12/18/2012

1.1

Updated to 2012.4 Vivado Design Suite.

Updated Appendix B, Debugging.

08/17/2011

1.0

Initial Xilinx release as product guide release. This document is based on ds768.