Slave I/O Signals - 2.1 English

AXI Interconnect LogiCORE IP Product Guide (PG059)

Document ID

PG059

Release Date

2022-05-17

Version

2.1 English

Table: AXI Infrastructure Core Slave I/O Signals lists the Slave Interface signals for the cores.

Table 2-33: AXI Infrastructure Core Slave I/O Signals
Signal Name	Direction	Default	Width	Description (Range)
s_axi_aclk	Input	REQ	1	Slave interface clock input. AXI Clock Converter and Data Width Converter core only.
s_axi_aresetn	Input	REQ	1	Slave interface reset input (active-Low). AXI Clock Converter and Data Width Converter core only.
s_axi_awid	Input	AXI3, AXI4: 0 AXI4-Lite: d/c	ID_WIDTH	Write Address Channel Transaction ID
s_axi_awaddr	Input	REQ	ADDR_WIDTH	Write Address Channel Address
s_axi_awlen	Input	AXI3, AXI4: 0 AXI4-Lite: d/c	AXI4: 8 AXI3: 4	Write Address Channel Burst Length (0–255)
s_axi_awsize	Input	AXI3, AXI4: REQ⁽¹⁾ AXI4-Lite: d/c	3	Write Address Channel Transfer Size code (0–7)
s_axi_awburst	Input	AXI3, AXI4: REQ⁽¹⁾ AXI4-Lite: d/c	2	Write Address Channel Burst Type code (0–2).
s_axi_awlock	Input	AXI3, AXI4: 0 AXI4-Lite: d/c	AXI4: 1 AXI3: 2	Write Address Channel Atomic Access Type (0, 1)
s_axi_awcache	Input	AXI3, AXI4: 0⁽²⁾ AXI4-Lite: d/c	4	Write Address Channel Cache Characteristics
s_axi_awprot	Input	0b000⁽³⁾	3	Write Address Channel Protection Bits
s_axi_awqos⁽⁴⁾	Input	AXI4: 0 AXI4-Lite: d/c	4	AXI4 Write Address Channel Quality of Service
s_axi_awregion	Input	AXI4: 0; AXI3, AXI4-Lite: d/c	4	AXI4 Write Address Channel address region index
s_axi_awuser⁽⁵⁾	Input	AXI3, AXI4: 0 AXI4-Lite: d/c	AWUSER_WIDTH	User-defined AW Channel signals
s_axi_awvalid	Input	REQ	1	Write Address Channel Valid
s_axi_awready	Output		1	Write Address Channel Ready
s_axi_wid	Input	AXI3: 0 AXI4, AXI4-Lite: d/c	ID_WIDTH	Write Data Channel Transaction ID for AXI3 masters
s_axi_wdata	Input	REQ	Data Width Converter: S_AXI_DATA_WIDTH; Others: DATA_WIDTH	Write Data Channel Data
s_axi_wstrb	Input	all ones	Data Width Converter: S_AXI_DATA_WIDTH/8; Others: DATA_WIDTH/8	Write Data Channel Byte Strobes
s_axi_wlast	Input	AXI3, AXI4: 0 AXI4-Lite: d/c	1	Write Data Channel Last Data Beat
s_axi_wuser⁽⁵⁾	Input	AXI3, AXI4: 0 AXI4-Lite: d/c	WUSER_WIDTH	User-defined W Channel signals
s_axi_wvalid	Input	REQ	1	Write Data Channel Valid.
s_axi_wready	Output		1	Write Data Channel Ready.
s_axi_bid	Output		ID_WIDTH	Write Response Channel Transaction ID.
s_axi_bresp	Output		2	Write Response Channel Response Code (0–3).
s_axi_buser⁽⁵⁾	Output		BUSER_WIDTH	User-defined B Channel signals.
s_axi_bvalid	Output		1	Write Response Channel Valid.
s_axi_bready	Input	REQ	1	Write Response Channel Ready.
s_axi_arid	Input	AXI3, AXI4: 0 AXI4-Lite: d/c	ID_WIDTH	Read Address Channel Transaction ID.
s_axi_araddr	Input	REQ	ADDR_WIDTH	Read Address Channel Address.
s_axi_arlen	Input	AXI3, AXI4: 0 AXI4-Lite: d/c	AXI4: 8 AXI3: 4	Read Address Channel Burst Length code (0–255).
s_axi_arsize	Input	AXI3, AXI4: REQ⁽¹⁾ AXI4-Lite: d/c	3	Read Address Channel Transfer Size code (0–7).
s_axi_arburst	Input	AXI3, AXI4: REQ⁽¹⁾ AXI4-Lite: d/c	2	Read Address Channel Burst Type (0–2).
s_axi_arlock	Input	AXI3, AXI4: 0 AXI4-Lite: d/c	AXI4: 1 AXI3: 2	Read Address Channel Atomic Access Type (0, 1).
s_axi_arcache	Input	AXI3, AXI4: 0⁽²⁾ AXI4-Lite: d/c	4	Read Address Channel Cache Characteristics.
s_axi_arprot	Input	0b000⁽³⁾	3	Read Address Channel Protection Bits.
s_axi_arregion	Input	AXI4: 0; AXI3, AXI4-Lite: d/c	4	AXI4 Read Address Channel address region index
s_axi_arqos⁽⁴⁾	Input	AXI4: 0 AXI4-Lite: d/c	4	AXI4 Read Address Channel Quality of Service.
s_axi_aruser⁽⁵⁾	Input	AXI3, AXI4: 0 AXI4-Lite: d/c	ARUSER_WIDTH	User-defined AR Channel signals.
s_axi_arvalid	Input	REQ	1	Read Address Channel Valid.
s_axi_arready	Output		1	Read Address Channel Ready.
s_axi_rid	Output		ID_WIDTH	Read Data Channel Transaction ID.
s_axi_rdata	Output		Data Width Converter: S_AXI_DATA_WIDTH; Others: DATA_WIDTH	Read Data Channel Data.
s_axi_rresp	Output		2	Read Data Channel Response Code (0–3).
s_axi_rlast	Output		1	Read Data Channel Last Data Beat.
s_axi_ruser⁽⁵⁾	Output		RUSER_WIDTH	User-defined R Channel signals.
s_axi_rvalid	Output		1	Read Data Channel Valid.
s_axi_rready	Input	REQ	1	Read Data Channel Ready.
Notes: 1.Xilinx recommends that AXI4 master devices drive their aw/rsize and aw/rburst outputs. Typically, a master device drives an aw/rsize value that corresponds to its interface data width, unless application requirements dictate otherwise. Typically, a master device drives its aw/rburst output to 0b01, which indicates an incremental (INCR) burst. 2.Xilinx recommends that master devices drive their aw/rcache outputs to 0b0011 to allow the AXI Interconnect core to pack data while performing width conversion and to allow store-and-forward in datapath FIFOs. 3.AXI protocol requires master devices to drive their aw/rprot output. If the aw/rprot signals are left undriven, it would default to all zeros and the transaction would be interpreted as secure. 4.Although the QOS signals are defined only by the AXI4 protocol specification, this interconnect IP core also propagates QOS signals for any SI slot configured as AXI3. 5.Signal not present on Data Width Converter core.