Timing Closure of AXI Memory-Mapped Connections Across SLRs in SSI Devices - 2.1 English

AXI Interconnect LogiCORE IP Product Guide (PG059)

Document ID
PG059
Release Date
2022-05-17
Version
2.1 English

This section describes how to apply the AXI Register Slice IP to pipeline the AXI pathways crossing between two SLR regions when targeting an SSI FPGA.

Assume two IP cores (A and B) with an AXI Memory-Mapped point-to-point connection that is known to cross from one Super Logic Region (SLR) to another:

Figure 4-17:      AXI Memory-Mapped Connections Across SLRs in SSI Devices

X-Ref Target - Figure 4-17

X18792-timing-closer-1.jpg

To facilitate timing closure of those AXI Memory-Mapped interfaces, crossing the SLRs with flop-to-flop paths is helpful. This can be accomplished by using the Vivado IP Integrator design entry to perform the following steps:

1.Add two AXI Register Slice IP cores in sequence to the AXI interface connection of IP cores A and B:

Figure 4-18:      Adding Register Slice Cores

X-Ref Target - Figure 4-18

X18793-register-slice.jpg

2.Double-click the first AXI Register Slice IP core A (which is connected to the AXI master interface of the source IP core A) and apply the following configuration options:

 

 

 

Figure 4-20:      AXI Register Slice A Options

X-Ref Target - Figure 4-19

X-Ref Target - Figure 4-20

register_slice_options_1.png

3.Add an XDC constraint to the design which places this AXI Register Slice IP core A in the same SLR as the source IP core A.

4.Double-click the second AXI Register Slice IP core B (which is connected to the AXI slave interface of the destination IP core B) and apply the following configuration options:

 

Figure 4-22:      AXI Register Slice B Options

X-Ref Target - Figure 4-21

X-Ref Target - Figure 4-22

register_slice_options_2.png

5.Add an XDC constraint to the design which places this AXI Register Slice IP core B in the same SLR as the destination IP core B.

See AXI Register Slices for a description of the register options of the AXI Register Slice IP.