The WRITE_ACCEPTANCE and READ_ACCEPTANCE parameters limit the number of current outstanding transactions of each type that the crossbar will accept, per SI slot. The crossbar maintains transaction counters to accommodate the maximum number of concurrent threads, depending on the SI-slot ACCEPTANCE limit or the number of different AWID/ARID values (2**THREAD_ID_WIDTH), whichever is smaller. The ACCEPTANCE limit parameters do not take into account the number of address transfers that might be accepted and stored in buffer modules, such as register slices and clock converters, that could be implemented along the address channel in the SI hemisphere, prior to arriving at the crossbar.
The WRITE_ISSUING and READ_ISSUING parameters limit the total number of current outstanding transactions of each type that the crossbar issues (with any ID value). The ISSUING limit parameters do not take into account the number of address transfers that might be accepted and stored in buffer modules, such as register slices and clock converters, that could be implemented along the address channel in the MI hemisphere, after being issued by the crossbar.
Regarding acceptance and issuing counters:
•A Write transaction is considered to be complete (counter decremented) when a bvalid/bready handshake completes at the crossbar.
•A Read transaction is considered to be complete when an rvalid/rready handshake completes at the crossbar in which rlast is asserted.
Write or Read transactions received at SI slots that have reached their acceptance limit, or that target an MI slot that has reached its issuing limit, are disqualified from arbitration so that the Write or Read arbiter, respectively, can continue to grant arbitration to other qualified SI slots, instead of stalling.
Increasing the value of an ACCEPTANCE or ISSUING parameter can increase data throughput by allowing Write and Read commands to be pipelined in connected slave devices, thus avoiding idle cycles on the Write and Read data channels. However, increasing the parameter values too much could lead to head-of-line blocking when multiple master devices access a shared slave.
When the tools copy the parameter values from the connected master and slave devices to the AXI Interconnect core:
•ISSUING parameters on connected master devices map to ACCEPTANCE parameters on the SI of the AXI Interconnect core
•ACCEPTANCE parameters on connected slave devices map to ISSUING parameters on the MI of the AXI Interconnect core
Note: For AXI4-Lite SI slots and MI slots, the ACCEPTANCE and ISSUING parameters, respectively, are ignored and only one outstanding transaction at a time is allowed.