The transaction ID signals that propagate from SI to MI (awid and arid) and back again (bid and rid) identify the original source of each transaction, and therefore, how responses received on the MI are to be routed back to the originating SI slot, and ultimately to the originating endpoint master across the interconnect topology of the system.
Endpoint master devices can optionally output awid and arid signals that the master device can use to select among multiple “threads” of transactions, as though the master IP core was comprised of multiple master devices internally. The “reordering depth” is the total number of ID values that can be generated by a master, and is assumed to be 2**idwidth, where idwidth is specified by the THREAD_ID_WIDTH parameter of each SI slot. Master devices with a reordering depth of one need not have any ID signals on their interface.
Transaction ordering is as follows:
•Transactions belonging to the same thread must be returned in order.
•Transactions among different threads can be returned out-of-order.
ID values among all the SI slots are made unique before propagating to any MI slot. The AXI Crossbar core prefixes a constant unique “master ID” value to the awid and arid signals sampled at each SI slot (if any).
A BASE_ID parameter associated with each SI slot allows the AXI Crossbar core to assign master IDs at compile time. Because endpoint master devices are not required to drive their assigned master ID on their own ID outputs, master devices do not need to be aware of their own assigned master ID values.
Master devices connected to the AXI Crossbar can use a different number of ID bits from one another. The AXI Crossbar only samples the ID bits defined by the THREAD_ID_WIDTH parameter for each SI slot. When assigning BASE ID values for each SI slot, all lower order bits in the range [THREAD_ID_WIDTH-1:0] must be zero. There must be no overlap among the ID ranges defined by BASE_ID and THREAD_ID_WIDTH across all SI slots. (These rules are enforced by the tools.)
The ID_WIDTH parameter on the AXI Crossbar core specifies the width of the complete transaction ID signal used by its internal transaction ordering logic and propagated by all MI slots. The value of ID_WIDTH must be high enough to include enough high-order bits (Master ID) to uniquely distinguish between all the SI slots. The tools automatically set the values of the ID_WIDTH and all BASE_ID parameters to satisfy these requirements.
After reserving enough low-order ID bits to accommodate the maximum THREAD_ID_WIDTH value, the crossbar sets the high-order bits of BASE_ID to be the binary SI-slot sequence number (0 up to 0xF), which is the "Master ID" value. IP integrator automatically sets the parameter ID_WIDTH to accommodate the Master ID plus the maximum THREAD_ID_WIDTH value [ceil_log2 NUM_SI + max(THREAD_ID_WIDTH)].
When configuring the AXI Crossbar as a stand-alone core in the Vivado® Integrated Design Environment (IDE), the value of the ID_WIDTH must exceed the maximum THREAD_ID_WIDTH by at least ceil_log2 NUM_SI. The ID_WIDTH is also used to determine the stride and total width of the ID signals on the SI of the crossbar, even though only a subset of those signals are sampled. Unsampled bit positions of the SI-side ID inputs should be tied-off to zero to avoid warnings during design compilation.
When two Interconnect instances are cascaded so that an MI slot of one instance connects to an SI slot of another instance, all ID signals produced by the upstream AXI Interconnect core are treated as though they are the thread ID bits of a connected master device. As with other master devices, the Crossbar in the downstream AXI Interconnect core prefixes the ID signals sampled from a cascaded SI slot with a unique master ID. This causes the ID width to grow as it propagates forward across a cascaded AXI Interconnect core topology.
All responses matching that master ID are routed back to the upstream AXI Interconnect core instance.