Clock Monitor - 6.0 English

The Clock Monitor feature is a part of the Clocking Wizard IP. It allows you to monitor the clock in a given system for clock loss or out-of-range errors. In Zynq or Zynq UltraScale devices, the clock monitored can be either a processing system (PS) clock or a programmable logic (PL) clock. In FPGAs, the clock monitored can be an arbitrary clock.

• Clock Stop : The clock is flat lined.

• Clock Glitch : Variation in the duty cycle of the clock.

• Overrun : The number of transitions in the clock is higher than expected.

• Underrun : The number of transitions in the clock is lower than expected.

Note: Overrun and Underrun are termed as out-of-range errors.

The IP provides scalable logic to monitor four clocks.

• Reference Clock Frequency : The reference clock frequency determines the frequency of the clock to be monitored.

• Channel Clock Frequency : You can choose the frequency of the clock to be monitored based on the value of reference clock.

• Tolerance : You can program the precision required to monitor the clock.

Note: Only integer values of tolerance are accepted.

• Enable_PLL/MMCM (0-1) : Enabling this option monitors the input clock to the MMCM/PLL.

Note: If the Enable_PLL/MMCM options are enabled in the IDE, ensure that the primary/secondary clock frequency does not exceed 300 MHz. Users cannot request user clock frequencies (USER_CLK_FREQ_0/1/2/3) beyond 300 MHz.